Pixel circuit and display device

ABSTRACT

When a selection TFT and a correction TFT are turned on, a data voltage of a data line is stored in a storage capacitor as a gate voltage of a driving TFT. After turning off the selection TFT, a voltage of a capacitor line SC falls, thereby turning on the driving TFT to supply a driving current to an organic EL element. The correction TFT is in the ON state before the capacitor line SC falls, and is turned off in the course of the fall of the line. Consequently, the capacitance of the correction TFT changes during the fall of the gate voltage, and the gradient of the gate voltage fall of the driving TFT is changed, thereby setting the gate voltage after the capacitor line SC falls in accordance with variation in threshold of the driving TFT. Particularly by disposing the driving TFT and the correction TFT adjacent to each other, the two TFTs are provided with the same properties to achieve effective correction.

TECHNICAL FIELD

The present invention relates to a pixel circuit including an emissiveelement, such as an organic EL element, and a display device having suchpixel circuits arranged in a matrix.

BACKGROND ART

Organic EL panels using organic EL elements as emissive elements havebeen known and actively developed. In such an organic EL panel, organicEL elements are arranged in a matrix, and light emission from theseorganic EL elements is individually controlled to display an image.Particularly, an organic EL panel of an active matrix type includes aTFT for display control for each pixel, and light emission is controlledfor each pixel by controlling operation of the TFT, thereby achieving avery high resolution display.

FIG. 13 shows an example of a pixel circuit in an organic EL panel ofthe active matrix type. A data line receiving a data voltage indicatingluminance of a pixel is connected to a gate of a driving TFT 12 throughan n-channel selection TFT 10 whose gate is connected to a gate line.The gate of driving TFT 12 is connected to one end of a storagecapacitor 14 whose other end is connected to a storage capacitor line SCfor holding a gate voltage of the driving TFT 12.

The driving TFT 12 has a source connected to an EL power source line,and a drain connected to an anode of an organic EL element 16, whosecathode is connected to a cathode power source.

Such pixel circuits are arranged in a matrix, and the gate line providedfor each horizontal line attains an H level with predetermined timing,thereby turning on the selection TFT 10 in that row. In this state, thedata voltage is sequentially supplied to the data line. Therefore, thedata voltage is supplied to, and stored in, the storage capacitor 14,and the voltage at this time is stored even after the gate line attainsan L level.

The driving TFT 12 operates in accordance with the voltage stored in thestorage capacitor 14, and the corresponding driving current is suppliedthrough the organic EL element 16 from the EL power source to thecathode power source, thereby causing the organic EL element 16 to emitlight in accordance with the data voltage.

The gate line sequentially attains the H level to sequentially supply anincoming video signal to the corresponding pixel as the data voltage,whereby the organic EL elements 16 arranged in a matrix emit light inaccordance with the data voltage, and an image is displayed with respectto the video signal.

In such a pixel circuit, however, variation in threshold voltage amongthe driving TFTs of the pixel circuits arranged in a matrix results invariation in luminance and deterioration in display quality. It isdifficult to obtain uniform properties of the TFTs forming the pixelcircuits for the entire display panel, and therefore to preventvariation in ON/OFF threshold.

It is therefore desired to suppress effects of the variation inthreshold among the driving TFTs on a display.

Various circuits to prevent the effects of difference in threshold ofthe TFTs have been proposed (such as JP-A-2002-514320).

However, this proposal requires a circuit to compensate for differencein threshold. Using such a circuit therefore increases the number ofelements in the pixel circuit, and decrease the aperture ratio. Additionof the circuit for compensation also requires a change in peripheralcircuits for driving the pixel circuit.

DISCLOSURE OF THE INVENTION

The present invention provides a pixel circuit to effectively compensatefor difference in threshold voltage of a driving transistor with asimple change.

The present invention according to one aspect provides a pixel circuitcomprising a selection transistor having one end connected to a dataline, and a control end receiving a selection signal, a correctiontransistor having one end connected to the other end of the selectiontransistor, and a control end connected to a first power source at apredetermined voltage, a driving transistor having a control endconnected to the other end of the correction transistor, and one endconnected to a second power source functioning as a current supplysource, a storage capacitor having one end connected to the control endof the driving transistor, and the other end connected to a pulsevoltage line, and an emissive element for emitting light caused by acurrent flowing through the driving transistor, wherein the correctiontransistor is switched on and off states in a process of turning on thedriving transistor by changing a voltage value of the pulse voltageline, thereby controlling a voltage of the control end of the drivingtransistor when it is turned on, and the driving transistor and thecorrection transistor are formed adjacent to each other.

Preferably, the data line and the power source line extend in a verticalscanning direction, and the correction transistor is formed between thedata line and the power source line.

The driving transistor is preferably formed on a side opposite to thecorrection transistor with the power source line located in between.

Preferably, a data voltage for turning on the correction transistor issupplied to the data line while the selection transistor is ON, avoltage corresponding to the data voltage is stored at the control endof the driving transistor, the selection transistor is turned offthereafter, and the voltage of the control end of the driving transistoris shifted by changing the voltage of the pulse voltage line in thisstate, thereby turning off the correction transistor and turning on thedriving transistor to cause a current in accordance with the datavoltage to flow into the driving transistor.

The first power source and the second power source are preferably thesame power source.

Preferably, the correction transistor and the driving transistor arep-channel transistors, and the pulse voltage line changes from a highlevel to a low level after the selection transistor is turned off.

The present invention according to another aspect provides a displaydevice including a plurality of pixels arranged in a matrix, each pixelcomprising a display element operating in accordance with suppliedpower, a selection transistor having a first conductive region connectedto a data line, and a control end receiving a selection signal, adriving transistor having a first conductive region connected to a powersource line for supplying power to the display element, a correctiontransistor having a control end connected to a first power source at apredetermined voltage, a first conductive region connected to a secondconductive region of the selection transistor, and a second conductiveregion connected to a control end of the driving transistor, and astorage capacitor having a first electrode connected to the control endof the driving transistor and the second conductive region of thecorrection transistor, and a second electrode connected to a pulsevoltage line. A voltage of the control end of the driving transistor ischanged in response to a change in a voltage of the pulse voltage line,and in accordance with the change, the correction transistor controlsthe voltage of the control end in accordance with an operation thresholdthereof when the driving transistor turns on. The correction transistorand the driving transistor are formed as transistors of the sameconductivity type, and at least a channel region of each of thecorrection transistor and the driving transistor is formed of asemiconductor layer polycrystallized through laser annealing, and thechannel regions thereof are disposed in close proximity to each other.

According to a further aspect of the present invention, in the abovepixel circuit or the display device, a channel length direction of thecorrection transistor and a channel length direction of the drivingtransistor are disposed in parallel to a scanning direction of aline-shaped pulse laser irradiated upon the polycrystallization laserannealing, and at least part of both channel regions of the correctiontransistor and the driving transistor are located on the same lineextending in a direction perpendicular to the scanning direction of thepulse laser.

In a display device according to a further aspect of the presentinvention, an arrangement may be employed in which the correctiontransistor and the driving transistor are formed as transistors of thesame conductivity type, and at least part of an active layer of thecorrection transistor is formed below the power source line with aninsulating layer disposed in between.

According to the present invention, in the above display device, thefirst power source may also be used as the power source line, and acontrol electrode of the correction transistor connected to the powersource line may be formed between the active layer of the correctiontransistor and a layer of the power source line. Further, the correctiontransistor may include an active layer formed between the data line andthe power source line to extend partially underlying at least one ofthese lines.

According to a further aspect of the present invention, in the abovedisplay device, the channel region of the correction transistor hasportions differing in channel width in the channel length directionthereof.

As described above, according to the present invention, the correctiontransistor is switched on and off states in the course of turning on thedriving transistor by changing the voltage value of the pulse voltageline, thereby controlling the voltage of the control end when thedriving transistor is ON. Consequently, the voltage varied in accordancewith the threshold voltage of the correction transistor can be set atthe control end of the corresponding driving transistor. Further,because the driving transistor and the correction transistor are formedadjacent to each other, the threshold voltages of the driving transistorand the correction transistor can be set at similar voltages, therebycompensating for the threshold voltage of the driving transistor withthe correction transistor, and achieving a uniform amount of currentsupplied to the emissive element.

The data line and the power source line extend in the vertical scanningdirection, the correction transistor is formed between the data line andthe power source line, and the driving transistor is formed opposite tothe correction transistor sandwiching the power source line, therebyachieving efficient arrangement, and maximizing the size of a displayelement, such as the emissive element, to implement a display devicehaving a high aperture ratio.

For example, an arrangement in which the active layer of the correctiontransistor is disposed below the power source line with an insulatinglayer arranged in between further enhances the design freedom ofarrangement within a pixel. When the control electrode (gate electrode)of the correction transistor is connected to the power source line, thesame voltage as the power source line is applied by the controlelectrode to the channel region thereof even though the active layer ofthe correction transistor is located below the power source line,thereby suppressing effects on operation of the transistor.

The degree of freedom in arranging transistors and the like within apixel can be also enhanced by providing the correction transistor withportions differing in the channel width in the channel length directionthereof.

With a change in voltage of the pulse voltage line, the drivingtransistor transitions from the OFF state to the ON state, and thecorrection transistor is switched on/off, whereby the capacitancethereof is changed. The level of the gate voltage of the drivingtransistor at which the correction transistor is switched on/off ischanged in accordance with a change in threshold of the correctiontransistor. The change in gate voltage of the driving transistor inaccordance with the change in the pulse voltage line depends on thecapacitance of the correction transistor, and therefore the gate voltageis varied in accordance with the variation in threshold of thecorrection transistor. Consequently, easy control can be achieved byequalizing the properties of the correction transistor and the drivingtransistor as much as possible for the sake of changing the gate voltageof the driving transistor to cancel the variation in threshold of thedriving transistor.

When the channel regions of the correction transistor and the drivingtransistor are both formed of a semiconductor layer polycrystallizedthrough laser annealing, the properties can easily be equalized bydisposing at least these channel regions in close proximity to eachother.

For example, when an active layer polycrystallized through laserannealing is used, the channel length directions of the correctiontransistor and the driving transistor are disposed in parallel to thescanning direction of a line-shaped pulse laser irradiated uponpolycrystallization laser annealing, so that the laser pulse can beirradiated a plurality of times in the channel length direction, whichsignificantly affects electrical mobility of the transistor, therebyreducing variation in properties of each transistor among pixels. Byarranging at least part of the channel regions of the correctiontransistor and the driving transistor juxtaposed on the same lineextending in the direction perpendicular to the scanning direction ofthe pulse laser, the channel regions of the two transistors areirradiated with the same laser beam, thereby achieving closer propertiesthereof.

When the first and second power sources are provided as the same powersource, the need to provide separate power source lines can beeliminated.

When the correction transistor and the driving transistor are bothprovided as p-channel transistors, the gate capacitance of the p-channeltransistor can effectively be used by the change in the pulse voltageline from the high level to the low level after the selection transistoris turned off.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a configuration of a pixel circuit according to anembodiment of the present invention.

FIG. 2 is a timing chart of signals applied to a gate line GL and acapacitor line SC according to the embodiment of the present invention.

FIG. 3 shows how a gate voltage V_(g24) is changed according to theembodiment of the present invention.

FIG. 4 is a diagram for describing a capacitor present in the pixelcircuit according to the embodiment of the present invention.

FIG. 5 shows an example of a planar configuration of a pixel accordingto the embodiment of the present invention.

FIGS. 6A and 6B schematically show cross sectional configurations takenalong lines A-A and B-B, respectively, in FIG. 5.

FIG. 7 shows an equivalent circuit per pixel obtained when a correctionTFT is multigated according to the embodiment of the present invention.

FIG. 8 is a schematic plan view showing an example of a layoutimplementing the equivalent circuit of FIG. 7.

FIG. 9 shows an equivalent circuit obtained when a selection TFT and thecorrection TFT are both multigated according to the embodiment of thepresent invention.

FIG. 10 shows an example of a layout implementing the equivalent circuitof FIG. 9.

FIG. 11 shows a different example of a layout from that shown in FIG.10.

FIG. 12 shows a further example of a circuit configuration according tothe embodiment of the present invention.

FIG. 13 shows a configuration of a conventional pixel circuit.

THE BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention will now be described withreference to the accompanying drawings.

FIG. 1 shows a configuration of a pixel circuit per pixel according toan embodiment. A data line DL extending in a vertical scanning directionis connected to a first conductive region (drain) of an n-channelselection TFT 20. The selection TFT 20 has a gate (control end)connected to a gate line GL extending in a horizontal scanningdirection, and a second conductive region (source) connected to a firstconductive region (source) of a p-channel correction TFT 22. Theselection TFT 20 may have a p-channel, and for the p-channel TFT, thepolarity (H level or L level) of a selection signal (gate signal)provided to the gate line GL will be inverted for driving thetransistor.

A control end (gate) of the correction TFT 22 is connected to a powersource line PL (voltage Pvdd), and a second conductive region (drain) isconnected to a control end (gate) of a p-channel driving TFT 24. Thegate of the driving TFT 24 is also connected to one end (firstelectrode) of a storage capacitor 28, whose other end (second electrode)is connected to a storage capacitor line (hereinafter referred to as a“capacitor line”) SC acting as a pulse voltage line driven by a pulsedvoltage. The capacitor line SC extends in the horizontal scanningdirection, as does the gate line GL. If another power source line isprovided to connect to the gate of the correction TFT 22, the timing toswitch off the correction TFT 22 from the ON state can be adjusted asdesired.

The driving TFT 24 has a first conductive region (source) connected tothe power source line PL extending in the vertical scanning direction,and a second conductive region (drain) connected to an anode of anorganic EL element 26. A cathode of the organic EL element 26 isconnected to a cathode power source CV at a predetermined low voltage.The cathode of the organic EL element 26 is usually shared by allpixels, and such a cathode is connected to the cathode power source CV.

In an organic EL panel, such pixel circuits are arranged in a matrix,and at the timing that a video signal is supplied on a correspondinghorizontal line, a gate line for that horizontal line attains an Hlevel, thereby turning on the selection TFT 20 in that row. As a result,the source of the correction TFT 22 attains a potential of the data lineDL.

The data line DL receives a data voltage. This data voltage Vdatacorresponds to the video signal for display at a corresponding pixel,and represents, for example, a range from white level to black level inthe voltage range of approximately 3 to 5 V. On the other hand, thevoltage Pvdd of the power source line PL is set at approximately 0 V.Consequently, when the selection TFT 20 is turned on and the datavoltage Vdata on the data line DL is applied to the correction TFT 22(in this example the source thereof), the correction TFT 22 is turnedon, and the data voltage Vdata is set at the gate (node Tg24) of thedriving TFT 24. In other words, a voltage of approximately 3-5 V is setat the gate of the driving TFT 24 in a period of writing the datavoltage Vdata to each pixel. The capacitor line SC connected to theother end of the storage capacitor 28 is set at approximately +8 V.

After such data voltage Vdata is thus written to the gate of the drivingTFT 24, the voltage of the capacitor line SC is reduced to, for example,−4 V. In response to such a reduction, the gate voltage of the drivingTFT 24 is lowered by approximately 12 V, and the driving TFT 24 isturned on, whereby the current in accordance with the data voltage issupplied to the organic EL element 26 from the power source line PLthrough the driving TFT 24, causing light emission.

Since the voltage of the capacitor line SC is decreased from +8 V toapproximately −4 V, a voltage of the drain (node Tg24) of the correctionTFT 22 changes from 3-5 V to basically a negative voltage in the orderof −9 V to −7 V (this voltage varies slightly as described hereinafter),and turns into an OFF state from an ON state. The gate capacitance ofthe correction TFT 22 is varied with such a turn-off of the correctionTFT 22, and therefore the timing at which the capacitance, i.e. athreshold Vth22 of the correction TFT 22, is changed has an influence onthe eventual gate potential of the driving TFT 24. Consequently,variation in a threshold voltage Vth24 of the driving TFT 24 can becompensated by the correction TFT 22.

Note that the driving TFT 24 is turned on and supplies a correspondingdriving current in accordance with a difference between the power sourcevoltage Pvdd and the gate voltage Vg24, i.e. Vgs24. When the voltageVgs24 exceeds the threshold voltage Vth24 determined by the propertiesof the TFT, the driving TFT 24 starts supplying a current, and theamount of the driving current is determined by the difference betweenthe gate voltage Vg24 and the threshold voltage Vth24. Meanwhile, it isdifficult to completely equalize the threshold voltage Vth24 of thedriving TFT 24 in each of a multitude of pixels arranged in a matrix ona substrate, and some variation in the threshold voltage Vth24 dependingon positions of the pixels cannot be avoided. Because the organic ELelement 26 emits light at a luminance in accordance with the amount ofsupplied driving current, the luminance of light emitted from each pixelvaries with the variation in the threshold voltage Vth24 of the drivingTFT 24. The configuration according to the present embodimentcompensates for the variation in luminance of emitted light with thechange in capacitance of the correction TFT 22.

The principles of compensating for the variation in luminance of emittedlight will be described with reference to FIGS. 2 and 3. FIG. 3 is anenlarged view of a falling edge of the capacitor line SC circled in FIG.2. Referring to FIG. 2, the gate line GL attains an active (H) levelwhen the corresponding row (horizontal line) is selected. In thisexample, the selection TFT 20 has an n-channel, the L level and H levelof the gate line GL are set approximately at −4 V and 8 V, respectively,and the voltage is set at 8 V when it is selected (activated).

On the other hand, a voltage V_(SC) of the capacitor line SC attains anH level for a period slightly longer than the selection (H level) periodof the gate line GL. In other words, the voltage attains the H levelbefore the gate line GL attains the H level, and attains the L levelafter the gate line GL attains the L level.

During the period the gate line GL is at the H level, the selection TFT20 and the correction TFT 22 corresponding to this gate line GL areturned on, and the data voltage Vdata supplied to the data line DL isapplied to the node Tg24 through the selection TFT 20 and the correctionTFT 22. In other words, the gate voltage V_(g24) of the driving TFT 24is set at the data voltage Vdata.

After the gate line GL attains the L level and the data voltage Vdata iswritten, the voltage of the capacitor line SC falls, and, in response tothe fall, the potential of the node Tg24 decreases, whereby thecorrection TFT 22 turns off in the course of time. The gate voltageV_(g24) of the driving TFT 24 becomes lower than the data voltage Vdataby a predetermined voltage in accordance with the decrease (12 V in thisexample; from 8 V to −4 V) of the capacitor line SC, and the TFT 24supplies the driving current in accordance with this voltage.

The correction TFT 22 is provided for each pixel, arranged adjacent tothe driving TFT 24 for that pixel, and formed through the same step asthe driving TFT 24. Particularly, the TFT properties can be made uniformby simultaneous radiation of the same laser pulse to the active regionsof the driving TFT 24 and the correction TFT 22 for polycrystallizationwhen, for example, polycrystalline silicon obtained by polycrystallizingamorphous silicon through laser annealing is used as active layers of,for example, the driving TFT 24 and the correction transistor 22 as wellas the selection TFT 20, as described hereinafter. The impurityconcentration doped to the active layer can be made substantially thesame. As a result, the driving TFT 24 and the correction TFT 22 havesubstantially the same threshold voltage. Because the gate of thecorrection TFT 22 is connected to the power source line PL (Pvdd=0 V inthis example), it changes from the ON state to the OFF state in responseto the decrease in the voltage V_(g24) at the node Tg24.

Thus, the correction TFT 22, which is a p-channel TFT, changes from theON state to the OFF state at the fall of the capacitor line SC, whilethe driving TFT 24 changes from the OFF state to the ON state. The gatecapacitance Cg of the TFT is changed depending on whether it is in theON state or the OFF state. Consequently, the change in the gate voltageV_(g24) of the driving TFT 24 is affected by the changes in the ON/OFFstate of the two TFTs 22 and 24. More specifically, the capacitance Cgis larger when the TFT is ON, and smaller when it is OFF. Because thecapacitance is larger in the ON state than in the OFF state, the voltagechange is affected by the capacitance change.

In other words, when the correction TFT 22 transitions from the ON stateto the OFF state, and the gate capacitance C_(g22) thereof is decreased,a gradient α of decrease in the voltage V_(g24) is increased.

Consequently, when a switch voltage at which the correction TFT 22 of agiven pixel is switched from the ON state to the OFF state is a “switchvoltage A” in FIG. 3, the voltage of the node Tg24 (gate voltageV_(g24)) changes as indicated by a solid line in the figure. Morespecifically, the gate voltage V_(g24) changes (decreases) at a firstgradient α₁ from the temporarily set data voltage Vdata before reachingthe switch voltage A, and changes (decreases) at a second gradient α₂after reaching the switch voltage A. When the driving TFT 24 is turnedon, the voltage changes (decreases) at a third gradient α₃. When apredetermined period is elapsed after the voltage of the capacitor lineSC attains the L level, the voltage V_(g24) is set at a correctionvoltage VcA.

The switch voltage at which the correction TFT 22 is switched from theON state to the OFF state is determined by the difference V_(gs22)between the power source voltage Pvdd=0, which is the gate voltage ofthe correction TFT 22, and the source voltage thereof. Consequently, theswitch voltages A and B are equal to a sum of the power source voltagePvdd and the absolute value of the threshold voltage V_(th22) of thecorrection TFT 22 (Pvdd+|V_(th22)|)

On the other hand, when the threshold voltage V_(th22) of the correctionTFT 22 is the “switch voltage B” lower than the “switch voltage A”, thegate voltage V_(g24) changes as indicated by a broken line in FIG. 3.More specifically, the gate voltage V_(g24) changes (decreases) at thefirst gradient α₁ from the temporarily set data voltage Vdata beforereaching the switch voltage B, and changes (decreases) at the secondgradient α₂ after reaching the switch voltage B. When the driving TFT 24is turned on, the voltage changes (decreases) at the third gradient α₃.When a predetermined period is elapsed after the voltage of thecapacitor line SC attains the L level, the voltage V_(g24) is set at acorrection voltage VcB.

Thus, even though the same data voltage Vdata is supplied at first tothe node Tg24, the eventual gate voltage V_(g24) of the driving TFT 24is set at a correction voltage Vc which takes a higher value for a lowerthreshold voltage.

As described above, the threshold voltage V_(th24) of the driving TFT 24corresponds to the threshold voltage V_(th22) of the correction TFT 22.As a result, when the threshold voltage V_(th24) of the driving TFT 24is “V_(th24)A”, the gate voltage V_(g24) is set at the correctionvoltage VcA corresponding to the threshold voltage V_(th24)A. When thethreshold voltage is “V_(th24)B”, the gate voltage V_(g24) is set at thecorrection voltage VcB corresponding to the threshold voltage V_(th24)B.The difference between the threshold voltage Vth24 and the correctedgate voltage V_(g24) remains the same whether the threshold voltage isV_(th24)A or V_(th24)B in this example. That is, as long as the samedata voltage Vdata is maintained through setting of the size of thecorrection TFT 22, the power source voltage Pvdd, the size of thedriving TFT 24, the capacitance Cs of the storage capacitor 28, and thelike, the difference between the threshold voltage V_(th24) and the gatevoltage V_(g24) can be fixed even though the threshold voltage V_(th24)of the driving TFT 24 varies with the pixel, thereby eliminating theeffects of variation in threshold voltage V_(th24) of the driving TFT24.

For such a compensation, the second gradient α₂ is preferably set totwice the value of the first gradient α₁. Such condition setting will bedescribed with reference to FIG. 3. Referring to FIG. 3, when thecorrection TFT 22 is ON, the capacitance C_(g22) thereof is greater thanin the OFF state, the effects of the change in pulse driving voltage onthe change in the gate voltage V_(g24) is suppressed, and the gradientα₁ is smaller. On the other hand, when the correction TFT 22 is off, thecapacitance C_(g22) is smaller, and the effects of the change in pulsedriving voltage are greater, whereby the gradient α₂ is greater. Becausethe gradient α₂ is set to twice the value of the gradient α₁, thedecrease in the gate voltage V_(g24) when the pulse driving voltageattains the L level is twice as big in the OFF state of the correctionTFT 22 than in the ON state.

More specifically, the TFT is formed so that a difference ΔV_(th24) inthreshold voltage between the two driving TFTs 24 is equal to adifference ΔV_(th22) in threshold voltage between the two correctionTFTs 22, and the gradient is doubled when the correction TFT 22 isswitched off from the ON state, whereby the relation ΔV_(th22)=ΔV_(th24)holds true, and a difference ΔVc between two correction voltages (VcAand VcB) is equal to ΔV_(th24).

In other words, referring to FIG. 3, all the following factors are equalto one another:

-   (i) a difference (ΔV_(th22)) between the switch voltages A and B of    the two correction TFTs 22-   (ii) a difference (ΔV_(th22)′) between the switch voltage B (the one    switched later: the lower voltage in this example) and the voltage    V_(g24)A of a node Tg24A in a pixel including the correction TFT 22    having the switch voltage A when the node Tg24B in the pixel reaches    the switch voltage-   (iii) a difference (ΔVth₂₄) in the switch voltage between the two    driving TFTs 24-   (Vi) a difference (ΔVc) between the correction voltages VcA and VcB.

Note that even when a sampling voltage, a voltage written as the datavoltage Vdata, is changed, the switch voltage difference ΔV_(th22)remains equal to the correction voltage difference ΔVc because thegradient is the same, so that the fluctuation in threshold voltage canalways be compensated.

Further, experiments have shown that the potential difference of thedata voltage is amplified twice in the correction voltage after thecompensating operation. As a result, the range of the data voltage canbe reduced, and a sufficient difference in gate voltage of the drivingTFT 24 can be maintained, thereby reducing the load of a circuit forsupplying the data voltage, and facilitating formation thereof.

As described above, the change in gate voltage of the driving TFT 24when the voltage of the capacitor line SC falls is affected particularlyby the gate capacitance C_(g22) of the correction TFT 22, the gatecapacitance C_(g24) of the driving TFT 24, the capacitance Cs of thestorage capacitor 28, and a parasitic capacitance Cw of a wiring line.

The mechanism of the above-mentioned change in the voltage V_(g24) willbe described based on the amount of movement of electric charges. It isdefined here that the capacitance of the storage capacitor 28 will bedenoted as Cs, the gate capacitance of the correction TFT 22 as C_(g22),the gate capacitance of the driving TFT 24 as C_(g24), the thresholdvoltage of the correction TFT 22 as V_(th22), the threshold voltage ofthe driving TFT 24 as V_(th24), and the capacitance Cs of the storagecapacitor 28 is equal to the gate capacitance C_(g22) of the correctionTFT 22.

-   (i) First, when the voltage of the capacitor line SC is decreased by    12 V while the gate voltage V_(g24) of the driving TFT 24 is equal    to Vdata, the voltage V_(g24) of the node Tg24 should also be    decreased by 12 V. Assuming that the voltage V_(g24) taking only    this change into consideration is denoted as V_(g24′), the equation    V_(g24)′=Vdata−12 is established.-   (ii) Assuming that the gate capacitance of the correction TFT 22 is    denoted as C_(g22), an amount Q_(f22) of charges flowing into the    storage capacitor 28 from the correction TFT 22 can be expressed as    follows:    Q _(f22) =C _(g22)×(Vdata−|V _(th22)|)

According to the present embodiment, the capacitance C_(g22) is equal toCs, and the voltage V_(g24) of the node Tg24 is increased by(Vdata−|V_(th22)|), as described above. Thus, the voltage V_(g24)″taking into this increase into consideration becomes:V _(g24)″=2Vdata−12−|V _(th22)|.

-   (iii) Further, electric charges also flow from the gate of the    driving TFT 24 into the storage capacitor 28. The amount Q_(f24) of    charges can be expressed as follows:    Q _(f24) =−C _(g24)′×(V _(g24) +|V _(th24)|)    wherein the eventual gate voltage of the driving TFT 24 is V_(g24),    the value C_(g24)′ is a difference in capacitance of the driving TFT    24 between ON and OFF states, derived from the equation    C_(g24)′=C_(g24)×⅔ using the Meyer's equation in SPICE simulator.-   (iv) The gate voltage V_(g24) of the driving TFT 24 can be regarded    as a voltage shifted by the amount of the electric charges Q_(f24)    flowing into the storage capacitor 28. Thus,

$\begin{matrix}{V_{g\; 24} = {{V_{g\; 24}}^{''} + {Q_{f\; 24}/C_{g\; 22}}}} \\{= {{V_{g\; 24}}^{''} - {{{C_{g\; 24}}^{\prime}\left( {V_{g\; 24} + {V_{{th}\; 24}}} \right)}/C_{g\; 22}}}}\end{matrix}$Rewriting the above equation, the eventual voltage V_(g24) is obtainedas follows:

(1 + C_(g 24)^(′)/C_(g 22))V_(g 24) = 2Vdata − 12 − V_(th 22) − C_(g 24)^(′)/C_(g 22))V_(th 24)

When V_(th22)=V_(th24)=V_(th), the voltage V_(g24) takes the followingvalue:V _(g24=−|) V _(th)|+(2Vdata−12)/(1+C _(g24) ′/C _(g22))

The second term on the right hand side in the above equation is a fixedvalue based on the layout dimension, the voltage V_(g24) is shifted byV_(th), and therefore the shift in the threshold voltage V_(th) of thedriving TFT 24, if any, can be compensated.

Strictly speaking, the parasitic capacitance of the wiring line mustalso be taken into consideration, and the values may be set inconsideration thereof. Further, when the power source voltage Pvdd isnot 0 V, that value may also be taken into consideration.

In addition, when the threshold voltage V_(th22) of the correction TFT22 differs from the threshold voltage V_(th24) of the driving TFT 24,the gate voltage V_(g24) is desirably shifted by the threshold V_(th24)of the driving TFT 24. To that end, the factor C_(g24)′/C_(g22) in theabove expression should be adjusted. However, because a big adjustmentis difficult, the TFTs are preferably formed to achieve the relationV_(th22)=V_(th24) as much as possible.

The relations among various capacitors in the pixel circuit according tothe embodiment of the present invention will further be described withreference to FIG. 4. To the pixel circuit according to the presentembodiment, various parasitic capacitances including the above-describedgate capacitance C_(g22) of the correction TFT 22, and the gatecapacitance C_(g24) of the driving TFT 24 are connected in addition tothe storage capacitor Cs. By way of example, capacitances, such as aparasitic capacitance C_(w1) between the power source line PL and theconnection point (node) Tg24 between the drain of the correction TFT 22and the gate of the driving transistor 24, and a parasitic capacitanceC_(w2) between the power source line PL and a connection portion betweenthe sources of the correction TFT 22 and the selection TFT 20, arepresent as illustrated in FIG. 4. The relation between the gradient α ofthe decline in the voltage V_(g24) of the node Tg24 in FIG. 3 and theseparasitic capacitances will be described. The gradient α₁ beforereaching the switch voltage (A or B) from the data voltage Vdata in FIG.3 can be expressed as:α₁ =Cs/(C _(w1) +C _(w2) +Cs+C _(g22))Electric charges flow into the storage capacitor Cs in the state wherepredetermined electric charges are charged in all these parasiticcapacitances (C_(w1), C_(w2), C_(g22)), and therefore the gradient α₁ ofthe decline in the gate voltage V_(g24) can be expressed as the aboveequation.

The gradient α₂ of the decline in the voltage V_(g24) at the node Tg24between the time the switch voltage is reached and the time the drivingTFT 24 is turned on can be expressed as:α₂ =Cs/(Cs+C _(w1))This is because the correction TFT 22 is turned off after reaching theswitch voltage, and the gate capacitance C_(g22) thereof and theparasitic capacitance C_(w2) between the power source line PL and itssource are electrically disconnected from the storage capacitor 28(whose capacitance is Cs).

Note that the value α₂ is set equal to 2×α₁. Therefore, by setting thecapacitance Cs of the storage capacitor 28 so that the capacitance Cs isequal to C_(g22)−C_(w1)+C_(w2), the gradient α₂ of the decline in thegate voltage Vg24 of the driving TFT 24 can be set to twice the gradientα₁ by switching off the correction TFT 22 from the ON state when thevoltage of the capacitor line SC falls, so that variation in thresholdvoltage of the driving TFT 24 can be properly compensated.

The gradient α₃ after the driving TFT 24 turns on shown in FIG. 3 can beexpressed as:α₃ =Cs/(Cs+C _(w1) +C _(g24))

The value C_(g24) is the gate capacitance of the driving TFT 24 asdescribed above, and is connected to the storage capacitor 28 by turningon the driving TFT 24. The gradient α₃ of the voltage drop is alsoaffected by this capacitance C_(g24). The timing t_(on24) at which thedriving TFT 24 turns on does not depend on the switch voltage of thedriving TFT 24, i.e. the threshold voltage V_(th24) thereof, asdescribed above, but is simultaneous in all pixels. More specifically,it is the timing when the gate voltage Vg24 in each pixel circuit issimultaneously decreased to the voltage lower by a voltage according toits own threshold voltage V_(th24) than the power source voltage Pvddcaused by each correction TFT 22 turning off at the timing in accordancewith variation in the threshold voltage V_(th22) thereof.

A layout of pixels each including such a pixel circuit will be describedwith reference to FIG. 5 and FIGS. 6A and 6B. FIG. 5 shows a schematicplanar configuration of a pixel, and FIGS. 6A and 6B show schematiccross sectional configurations taken along lines A-A and B-B,respectively, in FIG. 5.

On a transparent insulating substrate 100 of glass or the like, a bufferlayer 102 is formed. Semiconductor layers (120, 124, 28 e) formed ofpolycrystalline silicon on the buffer layer to constitute active layersof TFTs and a capacitor electrode are indicated by a broken line in FIG.5. In FIG. 5, the gate line GL, the capacitor line SC, the gateelectrode 22 g of the correction TFT 22, and the gate electrode 24 g ofthe driving TFT 24 formed of a refractory metal material, such as Cr,above the above-described semiconductor layers are indicated by adash-dotted line. The data line DL and the power source line PL providedabove the semiconductor layer and the above lines GL and SC and formedof a low resistance metal material, such as AL, and a metal wiring line24 w formed in the same layer as these lines are indicated by a solidline.

In the layout of FIG. 5, each pixel is located between the gate lines GLformed along a horizontal scanning (H) direction of a display device,and between the data lines DL formed substantially along a verticalscanning (V) direction of the display device. The power source line PLis formed in the vertical scanning direction (column direction of thematrix) substantially juxtaposed with the data line DL. In each pixelregion, the power source line extends between the data line DL and theorganic EL element 26 of the pixel connected to that data line DL. Asdescribed hereinafter, the selection TFT 20, the correction TFT 22, andthe storage capacitor 28 are disposed between the data line DL and thepower source line PL, and the driving TFT and the organic EL element 26are disposed between the power source line PL and the data line DL inthe next column.

The selection TFT 20 is formed near an intersection between the gateline GL and the data line DL. The gate line GL includes a projectedportion formed toward the pixel region, covering and crossing part ofthe semiconductor layer 120 extending along the gate line GL with a gateinsulating film 104 interposed therebetween. This portion projected fromthe gate line GL functions as the gate electrode 20 g of the TFT 20, andthe region of the semiconductor layer 120 covered with the gateelectrode 20 g functions as the channel region.

The correction TFT 22 connected to the selection TFT 20 is disposed sothat the channel length direction thereof runs along the direction inwhich the data line DL extends (vertical scanning direction) in a regionsandwiched by the data line DL and the power source line PL. The activelayer of the correction TFT 22 is formed below the data line DL tounderlie part of the data line DL. The storage capacitor 28 is disposedbetween the correction TFT 22 and the capacitor line SC disposed inclose proximity to the gate line GL in the next row, more specificallyalong the capacitor line SC. The driving TFT 24 is disposed in a region(on the side of the organic EL element region 26) opposite to the regionwhere the correction TFT 22 is formed sandwiching the power source linePL. At least a channel region 24 c of the semiconductor layer 124constructing the active layer thereof is positioned as close as possibleto a channel region 22 c of the correction TFT 22 according to thislayout.

In the present embodiment, the active layers of the selection TFT 20 andthe correction TFT 22, and the capacitor electrode 28 e of the storagecapacitor 28 are integrally formed of the single semiconductor layer120. (Naturally, they may also be provided as separate layerselectrically connected with one another through predetermined wiring.)

In the region for forming the selection TFT 20, the data line DL and thesemiconductor layer 120 are connected through a contact hole formedpenetrating the gate insulating film 104 and an interlayer insulatingfilm 106. The semiconductor layer 120 extends from a region locatedunder the data line DL (a region contacting the data line DL) to aposition underlying the power source line PL along the gate line GL, andfrom this underlying position extends below the power source line PL inthe vertical scanning direction along the direction in which the powersource line PL extends. Further, just before reaching a contact betweenthe gate electrode 22 g of the correction TFT 22 and the power sourceline PL, the semiconductor layer 120 bends in the direction parallel tothe extending direction of the gate line GL from the position locatedunder the power source line PL, and extends toward the data line DL.

In the region where the selection TFT 20 is formed, an impurity dopedregion of the semiconductor layer 120 connected to the data line DLfunctions as a first conductive region (such as a drain region 20 d),and an intrinsic region thereof underlying the gate electrode 20 g andwhere no impurities are doped functions as a channel region 20 c. Asecond conductive region (such as a source region 20 s) to whichimpurities of the same conductivity type as the first conductive regionare doped is formed on the opposite side sandwiching the channel region20 c.

The semiconductor layer 120 extending toward the data line DL from theportion underlying the power source line PL bends, in the direction thedata line DL extends, near a site where it crosses the data line DLagain (near the first conductive region 20 d of the selection TFT 20),and extends in the vertical scanning direction in a region between thedata line DL and the power source line PL, with at least part of thelayer 120 underlying the region where the power source line PL is formed(and partially underlying the data line DL in this example).

The region of the semiconductor layer 120 located along the data line DLforms the active layer of the correction TFT 22. Above this activelayer, the gate electrode 22 g of the correction TFT 22 is disposed withthe gate insulating film 104 interposed therebetween. The gate electrode22 g is connected to the power source line PL through a contact holeformed in the interlayer insulating film 106. The gate electrode 22 gextends toward the data line DL from the position contacting the powersource line PL, bends at a position overlapping the semiconductor layer120 (active layer of the correction TFT 22), extends in the directionthe data line DL extends, covers above the semiconductor layer 120, andis located below the data line DL and the power source line PLunderlying part of these layers.

The region of the semiconductor layer 120 covered with the gateelectrode 22 g functions as the channel region 22 c, which is not dopedwith impurities, of the correction TFT 22. With the channel region 22 cin between, a first conductive region (such as a source region 22 s inthis example) doped with impurities of the conductivity type differentfrom the selection TFT 20 is formed on the selection TFT 20 side, and asecond conductive region (a drain region 22 d in this example) dopedwith the impurities of the conductivity type same as the firstconductive region 22 s is formed on the capacitor line SC side. Becauseat least the channel region 22 c of the correction TFT 22 is providedbelow, and partly underlying, the data line DL and the power source linePL, the correction TFT 22 can be efficiently disposed in a very smallregion between the data line DL and the power source line PL. Further,the channel region 22 c is electrically shielded from the data line DLby disposing the gate electrode 22 g between layers of the channelregion 22 c and of the data line DL and the power source line PL,thereby preventing the data signal applied to the data line DL fromaffecting operation of the correction TFT 22. Further, because at leastthe gate electrode 22 g of the correction TFT 22 is connected to thepower source line PL, the voltage applied to the channel region 22 c issubstantially the same in the arrangement where the active layer,particularly the channel region 22 c, of the correction TFT 22 isprovided underlying the power source line PL as in the arrangement wherethe channel region 22 c is covered with the gate electrode 22 g.Consequently, it is also possible to provide a major portion of theactive layer of the correction TFT 22 under the power source line PL,and such an arrangement can maximize the aperture ratio in each pixel,i.e. the area for forming the organic EL element 26 contributing tolight emission.

The semiconductor layer 120 is patterned to extend from the region forforming the second conductive region of the correction TFT 22 toward thecapacitor line SC, bend at a site crossing the capacitor line SC, andunderlie the capacitor line SC in the extending direction of thecapacitor line SC, i.e. the horizontal scanning direction, with the gateinsulating film 104 interposed therebetween. The region of thesemiconductor layer 120 underlying the capacitor line SC functions asthe capacitor electrode (first electrode) 28 e, and the region includingthe capacitor line SC (second electrode) and the capacitor electrode 28e disposed opposite to each other sandwiching the gate insulating film104 functions as the storage capacitor 28.

Between the second conductive region 22 d of the correction TFT 22 andthe capacitor electrode 28 e of the storage capacitor 28, the metalwiring line 24 w is connected via a contact hole formed through theinterlayer insulating film 106 and the gate insulating film 104. Themetal wiring line 24 w is formed along the extending direction of thecapacitor line SC, and connected to the gate electrode 24 g of thedriving TFT 24 via a contact hole formed through the interlayerinsulating film 106.

The gate electrode 24 g of the driving TFT 24 extends from the regioncontacting the metal wiring line 24 w toward the gate line GL for itsown row (upward in the figure), crosses under the power source line PLalong the way, and extends on the organic EL element 26 side of thepower source line PL in the extending direction of the power source linePL.

The power source line PL bends toward the data line DL from near theregion contacting the gate electrode 22 g of the correction TFT 22,bends again toward the organic EL element 26 near the above-describedmetal wiring line 24 w to circumvent the region where the line 24 w isformed, and extends in the vertical scanning direction toward the pixelin the next row from near the region contacting the semiconductor layer124 constituting the active layer of the driving TFT 24. The driving TFT24 is formed in a space created between the organic EL element 26 andthe power source line PL because the power source line PL approaches thedata line DL.

In the semiconductor layer 124 constituting the active layer of thedriving TFT 24, the channel region 24 c is formed in a region coveredwith the overlying gate electrode 24 g, a first conductive region (asource region 24 s in this example) is formed on the side connecting tothe power source line PL, and a second conductive region (a drain region24 d in this example) is formed on the side connecting to the organic ELelement 26. The channel region 24 c is an intrinsic region to which noimpurities are doped, and the first and second conductive regions (24 sand 24 d) provided on opposite sides thereof are doped with theimpurities of the same conductivity type as that of the above-describedcorrection TFT 22. The first conductive region 24 s of the driving TFT24 is connected to the power source line PL via a contact hole formedthrough the interlayer insulating film 106 and the gate insulating film104. The second conductive region 24 d of the driving TFT 24 isconnected to a connection electrode 24 e formed of the same material as,for example, the above-described power source line PL, via a contacthole formed through the interlayer insulating film 106 and the gateinsulating film 104.

As illustrated in FIGS. 6A and 6B, a planarization insulating layer 108of an organic resin or the like to planarize the upper surface is formedover the entire substrate covering the data line DL, the power sourceline PL, the above-described metal wiring line 24 w, and the connectionelectrode 24 e. In the planarization insulating layer 108, a contacthole is formed in a region for forming the connection electrode 24 econnected to the above-described driving TFT 24. Through this contacthole, a first electrode 262 (an anode in this example) of the organic ELelement 26 formed on the planarization insulating layer 108 and theconnection electrode 24 e are connected. When the connection electrode24 e is not provided, the first electrode 262 of the organic EL element26 and the second conductive region 24 d are directly connected byforming a contact hole penetrating the planarization insulating layer108, the interlayer insulating film 106, and the gate insulating film104 in the region where the second conductive region 24 d of the drivingTFT 24 is formed.

As illustrated in FIG. 6B, the organic EL element 26 includes anemissive element layer 270 provided between the first electrode 262formed as an individual pattern for each pixel on the substrate side andconnected to the driving TFT 24 and a second electrode 264. The firstelectrode 262 can be formed of a transparent conductive metal oxide orthe like, such as ITO (indium tin oxide), and functions as an anode(hole injection electrode) in this example. The second electrode 264 canbe formed of a metal material with a small work function, such as Al andAg, or have a multi-layer structure composed of such a metal materialand ITO described above, and functions as a cathode (electron injectionelectrode). Note that an edge portion of the first electrode 262 formedas an individual pattern for each pixel is covered with a secondplanarization insulating layer 110 formed on top of the planarizationinsulating layer 108, thereby preventing short-circuiting between thefirst electrode 262 and the second electrode 264 provided on theemissive element layer 270 formed as a very thin layer.

The emissive element layer 270 has a three-layer structure composed of ahole transport layer 272, an emissive layer 274, and an electrontransport layer 276 in this example. It is not limited to such athree-layer structure, and it may be formed as a single layer havinglight emissive function, or as a multi-layer structure including twolayers or more than four layers. When a multi-layer structure is usedfor the emissive element layer 270, all layers may be shared by allpixels, or some or all layers may be formed as an individual pattern foreach pixel as in the example of FIG. 6B where only the emissive layer274 is formed as an individual pattern similarly to the first electrode262.

In the thus configured organic EL element 26, according to the presentembodiment, a current supplied from the power source line PL through thedriving TFT 24 to the first electrode 262 flows between the electrode262 and the second electrode 264, causing light emission in the emissiveelement layer at the luminance in accordance with the amount of current.Light is emitted when emissive particles excited by recombination ofholes injected from the first electrode 262 and electrons injected fromthe second electrode 264 in the emissive element layer return to theground state. In this example, light is transmitted through thetransparent first electrode 262 and substrate 100 to exit outside fromthe substrate, and is observed.

In the layout of the present embodiment, the above-described correctionTFT 22 and the driving TFT 24 are arranged as close as possible to eachother sandwiching the power source line PL as described above.Particularly, the channel region 22 c of the correction TFT 22 and thechannel region 24 c of the driving TFT 24 are arranged so that at leastpart of the channel regions thereof are juxtaposed in the verticalscanning direction.

The active layer of each TFT formed in the pixel in the presentembodiment is formed of a low temperature polycrystalline silicon (LTPS)layer obtained through polycrystallization annealing by sequentiallyirradiating an amorphous silicon layer formed by plasma CVD or the likewith a line-shaped pulse laser beam (see FIG. 5) set so that itslongitudinal direction coincides with the horizontal scanning direction,and shifted by a predetermined pitch in its width direction. Thescanning direction of the laser beam coincides with the width directionof the laser beam and the vertical scanning direction, which is thedirection in which the data line DL and the like extend. As shown inFIG. 5, the respective channel regions 22 c and 24 c of the correctionTFT 22 and the driving TFT 24 are disposed so that their channel lengthdirection coincides with the extending direction of the data line DL andthe like, i.e. the scanning direction of the laser beam. Consequently,each of the channel regions 22 c and 24 c is reliably irradiated with alaser beam a plurality of times in the channel length directiontraversing the channel (in the channel width direction) by setting thescanning pitch of the laser beam smaller than the channel lengths of thecorrection TFT 22 and the driving TFT 24. As a result, even if theenergy of each laser beam is varied, variation in the total amount ofenergy received in the entire channel length direction can be reduced ineach pixel because each of the channel regions 22 c and 24 c isirradiated with a plurality of laser beams.

When the polycrystalline silicon layer formed through the so-calledlaser annealing is used for the active layer of the TFT, thepolycrystalline state substantially affecting the properties(particularly the threshold) of the TFTs can be easily equalized betweenthe correction TFT 22 and the driving TFT 24 by disposing the channelregions 22 c and 24 c in close proximity to each other so that theregions to be the channel regions 22 c and 24 c of the correction TFT 22and the driving TFT 24 are simultaneously irradiated with the same pulselaser beam.

One irradiation area of the line-shaped pulse laser is sized, forexample, 10 cm to 30 cm long in the longitudinal direction of the pulseand approximately 300 μm in the pulse width direction. The scanningpitch of the thus sized pulse laser is, for example, on the order of 25μm. In other words, the amorphous silicon is polycrystallized byshifting the irradiation position of the pulse laser by 25 μm. Further,each of the channel regions 22 c and 24 c of the correction TFT 22 andthe driving TFT 24 can be irradiated with the same pulse laser beam bydisposing, not only in close proximity to each other, but also at leastpart of the channel regions 22 c and 24 c to be juxtaposed on the sameline extending in the direction crossing the vertical scanningdirection. Further, by setting each of the correction TFT 22 and thedriving TFT 24 to have the channel length of at least 30 μm or longer,preferably 40 μm or longer, the channel regions 22 c and 24 c of the twoTFTs can be reliably irradiated with at least one or more of the samepulse laser beam by scanning the channel formation regions with theabove-sized pulse laser by the above-described pitch along the verticalscanning direction of the pixel.

Further, for simultaneous doping of the impurities of the sameconductivity type into the semiconductor layers 120 and 124 using eachof the gate electrodes 22 g and 24 g as a mask, impurity dopingconditions (doping density, doping energy, and the like) can beequalized because the formation areas are very close to each other.Thus, also in this respect, the properties of the correction TFT 22 andthe driving TFT 24 can be equalized.

In the above-described layout within the pixel region, circuit elements,such as the data line DL, the power source line, and the TFTs 20, 22,and 24, are disposed in the region on one side (left side in the pixelof FIG. 5) in the horizontal scanning direction of the pixel region,while the organic EL element 26 is disposed on the other side (rightside in the pixel of FIG. 5), thereby achieving efficient arrangement asa whole. More specifically, such a layout can provide the organic ELelement 26 with the maximum possible area within each pixel region,contributing to improvement in aperture ratio of the display device.Further, when lifetime of each pixel is equalized by varying the pixelarea for each color of emitted light in view of light emissionefficiency and the required luminance, it is possible to easily changeonly the area of the organic EL element 26 without changing the layoutand areas of the TFTs 20, 22, and 24, the storage capacitor 28, and thelike, so that design efficiency can be improved.

For the layout illustrated in FIG. 5, the so-called delta arrangement isemployed, in which the pixels of the same color among the pixelsarranged in a matrix are shifted for each row in the horizontal scanningdirection by a predetermined pitch. When a single data line DL suppliesthe data signal Vdata to the pixels of the same color, the data line DLextends meandering in the column direction of the matrix, as illustratedin FIG. 5, to be connected to the selection TFT 20 of each of the pixelsof the same color alternately arranged on the right and left sides ofthe line. Because such a layout is employed, in the pixel of the rowsubsequent to that shown in FIG. 5, the above-described organic ELelement 26 is disposed on the left side of the pixel, and the TFTs 20,22, and 24, and the like are on the right side of the pixel, as opposedto the layout of FIG. 5. Naturally, the above-described layout is notlimited to the delta arrangement, and is also applicable to the stripearrangement, in which the organic EL element and the TFTs and the likefor controlling the element are not horizontally inverted in positionfor each row.

In the correction TFT 22 of the present embodiment, the width of thechannel region 22 c (channel width) formed of the semiconductor layerchanges in the channel length direction as illustrated in FIG. 5. Morespecifically, in FIG. 5, the width is increased on the side close to theselection TFT 20 (upper side of the figure), and decreased on the sideconnected to the storage capacitor 28 and the driving TFT 24 (lower sideof the figure). By thus providing the correction TFT 22 with the portionhaving the width varying in its channel length direction at least fromother portions, the degree of freedom in arranging the correction TFT 22can be enhanced. As the property of the correction TFT 22, the smallestchannel width can be regarded as the standard. Such enhancement indegree of freedom in arranging the correction TFT 22 allows efficientlayout of other circuit elements, such as the gate electrode 24 g of thedriving TFT 24. For increasing the degree of freedom in arrangement, thewidth of the semiconductor layer forming the channel region (channelwidth direction) is preferably varied, and the degree of freedom inarrangement can further be enhanced by varying the channel width ofother elements, such as the selection TFT 20 and the driving TFT 24.

As described above, the pixel circuits according to the presentembodiment are arranged in a matrix to form a display device. In mostcases, the pixel region including the organic EL element and aperipheral driver circuit for driving each pixel located in theperiphery thereof are formed on a glass substrate. An organic EL panelis formed according to the following procedure. Circuit elements otherthan the organic EL element in the pixel region and the peripheraldriver circuit are first formed on the substrate, the organic EL elementis formed above these circuit elements, and a sealing substrate isbonded to the glass substrate 100 covering the substrate from theelement side. Note that the pixel circuit of the present embodiment isnot only used in such an organic EL panel, but can also be applied tovarious other display devices. Particularly, similar effects can beenjoyed in the application into the device in which a display element ofa current driving type and a circuit (TFT) for controlling this elementare formed for each pixel.

In the present embodiment, the selection TFT 20 and the correction TFT22 are preferably multigated. This is because it is effective to reducea leakage current often observed particularly in TFTs having apolycrystalline silicon layer as an active layer. The leakage current isa current flowing toward the data line DL through the correction TFT 22and the selection TFT 20 when these TFTs are off in the presentembodiment, and can be suppressed by multigating these TFTs. Only thecorrection TFT 22 may be multigated, as illustrated in FIG. 7, or onlythe selection TFT 20 may be multigated. Both of the TFTs may, of course,be multigated as illustrated in FIG. 9.

FIG. 7 is an equivalent circuit diagram of the circuit in which thecorrection TFT 22 is multigated, and FIG. 8 is a plan view showing anexample of a layout implementing the equivalent circuit. In the exampleof FIG. 7, a so-called double gate structure is employed for thecorrection TFT 22. More specifically, two TFTs, namely a firstcorrection TFT 22-1 whose drain is connected to the node Tg24 and asecond correction TFT 22-2 provided between the first correction TFT22-1 and the selection TFT 20, are provided between the node Tg24 andthe selection TFT 20. The gates of the first and second correction TFTs22-1, 22-2 are both connected to the power source line PL, and thesource and drain of each of the first and second correction TFTs 22-1,22-2 are electrically connected in series between the selection TFT 20and the node Tg24. Such a connection enhances off-leakage tolerancebetween the driving TFT 24 and the selection TFT 20, thereby effectivelypreventing the gate voltage V_(g24) of the driving TFT 24 stored in thestorage capacitor 28 from leaking to the data line DL to deviate from aproper value.

More specifically, by dividing the correction TFT 22, a voltage V_(s20)of the selection TFT 20 on the source side (the source voltage V_(d22-2)of the correction TFT 22-2) and the voltage V_(g24) of the node Tg24 aredivided at a connection node between the first and second correctionTFTs 22-1 and 22-2, whereby a voltage Vm of a value in between becomes asource voltage of the first correction TFT 22-1. The off-leakage currentof the TFT is reduced by approximately one digit when the drain-sourcevoltage Vds of the TFT is decreased by 1 V. Consequently, division ofthe correction TFT 22 contributes to decrease in the drain-sourcevoltage Vds of the first correction TFT 22-1 whose drain is connected tothe node Tg24, thereby reducing the off-leakage current.

When the correction TFT 22 is multigated as illustrated in FIG. 7, thechannel region of the first correction TFT 22-1 whose conductive region(drain in this example) is connected to the gate of the driving TFT 24need not be sized equal to the channel region of the other TFT, such asthe second correction TFT 22-2.

When, for example, the channel region of the first correction TFT 22-1is sized smaller than that of the second correction TFT 22-2, a gatecapacitance Cg22-1 of the first correction TFT 22-1 can be decreased. Ifa large amount of electric charges flow into the storage capacitor 28from the gate capacitor Cg22 when the correction TFT 22 is turned off,the potential of the node Tg24 is maintained at a high value for a longtime, lowering the speed of voltage decline following the fall of thecapacitor line SC. As a result, by decreasing the channel size of thefirst correction TFT 22-1, the amount of electric charges flowing intothe storage capacitor 28 from the gate capacitor Cg22-1 of the firstcorrection TFT 22-1 when it is off is reduced, thereby achieving fastdecline of the voltage at the node Tg24. In this case, the relationW1×L1<W2×L2 is preferably satisfied wherein the channel length andchannel width of the channel region of the first correction TFT 22-1 aredenoted as L1 and W1, respectively, and the channel length and channelwidth of the channel region of the second correction TFT 22-2 aredenoted as L2 and W2, respectively.

The channel length L1 of the first correction TFT 22-1 is minimized, butlong enough to at least satisfy the requirement of off-leakagereduction, while the channel width W1 thereof has the allowable maximumlength in view of layout restrictions. Although the longer channellength L2 of the correction TFT 22-2 contributes to slower flow ofelectric charges to the node Tg24 from the gate capacitor Cg22-2 of thesecond correction TFT 22-2, it will increase the on-resistance of theTFT, resulting in a longer data writing period. Consequently, the valueof L2/W2 is preferably small, i.e. the width W2 is increased for thelonger L2. Therefore, in this respect also, it is also preferable tosatisfy the above relation of W1×L1<W2×L2.

FIG. 8 is a planar configuration of a layout example in which thecorrection TFT 22 is multigated as described above. While, in theexample of FIG. 8 as well, the active layers of the selection TFT 20 andthe correction TFT 22 are integrally formed of the same conductivelayer, the semiconductor layer forming the active layers of the firstand the second correction TFTs 22-1 and 22-2 is labeled with the numeral122 in the figure for illustration purposes. The semiconductor layer 122extends toward the adjacent row (downward in the figure) along the dataline DL as in the layout of FIG. 5 described above.

The gate electrodes 22 g (22 g 1 and 22 g 2) of the correction TFTs 22-1and 22-2 are shared and connected to the power source line PL in aregion located below the power source line PL. The gate electrode 22 gextends in the horizontal scanning direction toward the data line DLfrom a position contacting the power source line PL, and a regioncrossing over the active layer 122 functions as the gate electrode 22 g2 of the second correction TFT 22-2. From here it extends to the regionwhere the data line DL is formed, and folds back immediately aftercrossing the data line DL to extend under the data line DL. Near aregion crossing under the data line DL, the gate electrode 22 g extendsagain toward the pixel in the next row along the extending direction ofthe data line DL to cover above the active layer 122, and a regionoverlapping the active layer 122 functions as the gate electrode 22 g 1of the first correction TFT 22-1. The gate electrode 22 g 1 of the firstcorrection TFT 22-1 is formed between layers of the power source line PLand the active layer 122, and electrically shields the active layer 122from the power source line PL and the data line DL provided above.

By thus patterning the gate electrode 22 g to fold back in the U-shape,the upper part of the semiconductor layer 122 extending in the verticalscanning direction along the data line DL is covered at, for example,two sites, so that channel regions 22 c 2 and 22 c 1 can be formed atthe portions covered with the gate electrode 22 g. In the semiconductorlayer 122, a source region 22 s 2, the channel region 22 c 2 (the regionbelow the gate electrode 22 g 2), and a drain region 22 d 2 of thesecond correction TFT 22-2 are formed in this order from the side of thesecond correction TFT 22-2 connecting to the selection TFT 20, and asource region 22 s 1, the channel region 22 c 1 (the layer below thegate electrode 22 g 1), and a drain region 22 d 1 of the firstcorrection TFT 22-1 are formed. The drain region 22 d 1 of the firstcorrection TFT 22-1 is connected to the capacitor electrode 28 e of thestorage capacitor 28 (the same semiconductor layer), and to the gateelectrode 24 g of the driving TFT 24 through the metal wiring line 24 e.

The layout as illustrated in FIG. 8 can minimize an increase in areawhere the element is disposed even if the correction TFT 22 ismultigated (double-gated in this example)

FIG. 9 shows a circuit configuration example in which theabove-described selection TFT 20 is also multigated in addition to thecorrection TFT 22. FIG. 10 is a plan view illustrating an actual layoutexample when the circuit configuration of FIG. 9 is implemented. In theexample of FIG. 9, the selection TFT is composed of two selection TFTs20-1 and 20-2 connected in series to the data line DL. The gates of thetwo selection TFTs 20-1 and 20-2 are both connected to the gate line GL.

The selection TFT 20 can be easily multigated by adding a simple changeto the layout of a single-gate selection TFT 20 illustrated in FIG. 5and the like. For example, as also illustrated in FIG. 10, thesemiconductor layer 120 forming the active layer of the selection TFT 20is U-shaped, extending from the data line DL and folding back at thepower source line PL near a region for forming the selection TFT 20.Consequently, the gate electrode 20 g protruding from the gate line GLmay be patterned to further extend as indicated by a dotted line in FIG.10 to overlap above the semiconductor layer 120 folding back from thepower source line PL. By thus extending the gate electrode 20 g to formthe gate electrodes 20 g 1 and 20 g 2 at the portion of the U-shapedfolding semiconductor layer 120 closer to the gate line GL and at theturn-back portion, respectively, and forming the channel regions 20 c 1and 20 c 2 thereunder, the selection TFT 20 of the double gate typewhose active layers are electrically connected in series to the dataline DL can easily be formed. As further illustrated in FIG. 10, aselection TFT 20 of a triple gate type in which three active layersthereof are connected in series to the data line DL can be obtained byproviding a projecting portion in the horizontal scanning direction inthe middle of the gate electrode 20 g, and covering the upper layer ofthe base portion of the U-shaped active layer with the projectingportion.

FIG. 11 illustrates another layout example of a multigated(double-gated) selection TFT 20. In the layout of FIG. 11, two gateelectrodes 20 g 1 and 20 g 2 are formed juxtaposed projecting from thegate line GL, which extends in the horizontal scanning direction, towardthe semiconductor layer 120 disposed from the region contacting the dataline DL in the horizontal scanning direction along the gate line GL. Inthis example, the channel regions 20 c 1 and 20 c 2 of the multigatedselection TFT 20 are disposed juxtaposed in the horizontal scanningdirection which is the extending direction of the gate line GL.

As described above, the off-leakage current can further be effectivelysuppressed by multigating the selection TFT 20 in addition to thecorrection TFT 22.

FIG. 12 illustrates a further circuit configuration example. In theequivalent circuit configuration per pixel illustrated in FIG. 12, thedata line DL is connected to one end (first conductive region, such asthe drain) of the selection TFT 20, and between the other end (secondconductive region, such as the source) of the selection TFT 20 and thefirst conductive region (such as the source) of the above correction TFT22, a leakage current suppression TFT 30 having a gate connected to thecapacitor line SC is further provided. The leakage current suppressionTFT 30 has an n-channel, and the polarity is opposite to that of thecorrection TFT 22.

The leakage current suppression TFT 30 is turned on when the capacitorline SC is at the H level, and turned off when it is at the L level.Consequently, it is in the ON state while the gate line GL is at the Hlevel, and therefore no problems arise by writing the data voltage Vdataof the data line DL into the gate of the driving TFT 24. On the otherhand, after data writing is complete, the TFT is turned off because thecapacitor line SC falls to the L level. More specifically, when thecapacitor line SC falls and the gate potential of the driving TFT 24becomes a low voltage, the leakage current suppression TFT 30 maintainsthe OFF state, thereby effectively suppressing the leakage currentflowing from the data line DL toward the gate of the driving TFT 24 inthis state. As a result, uniformity in luminance of light emitted fromeach of a plurality of pixels in a display device can be furtherenhanced. While reduction in the off-leakage current can be furtherpursued by multigating the correction TFT 22 in the configuration ofFIG. 12, an increase in circuit elements causes a decline in apertureratio. Therefore, it is preferable to decide whether or not to multigatethe correction TFT within a range maximizing the aperture ratio andachieving uniform luminance of light emitted form each pixel.

INDUSTRIAL APPLICABILITY

The invention is applicable to a display device and the like including adisplay element for each pixel.

1. A pixel circuit, comprising: a selection transistor having one endconnected to a data line, and a control end receiving a selectionsignal; a correction transistor having one end connected to the otherend of the selection transistor, and a control end connected to a firstpower source at a predetermined voltage; a driving transistor having acontrol end connected to the other end of the correction transistor, andone end connected to a second power source functioning as a currentsupply source; a storage capacitor having one end connected to thecontrol end of the driving transistor, and the other end connected to apulse voltage line; and an emissive element for emitting light caused bya current flowing through the driving transistor, wherein the correctiontransistor is switched between on and off states in a process of turningon the driving transistor by changing a voltage value of the pulsevoltage line, thereby controlling a voltage of the control end of thedriving transistor when it is turned on, and the driving transistor andthe correction transistor are formed adjacent to each other, wherein adata voltage for turning on the correction transistor is supplied to thedata line while the selection transistor is ON, a voltage correspondingto the data voltage is stored at the control end of the drivingtransistor, the selection transistor is turned off thereafter, and thevoltage of the control end of the driving transistor is shifted bychanging the voltage of the pulse voltage line in this state, therebyturning off the correction transistor and turning on the drivingtransistor to cause a current in accordance with the data voltage toflow into the driving transistor.
 2. A pixel circuit according to claim1, wherein the correction transistor and the driving transistor arep-channel transistors, and the pulse voltage line changes from a highlevel to a low level after the selection transistor is turned off.
 3. Apixel circuit according to claim 1, wherein active layers of thecorrection transistor and the driving transistor are formed ofpolycrystalline semiconductor obtained by polycrystallization laserannealing, and a channel length direction of the correction transistorand a channel length direction of the driving transistor are disposed inparallel to a scanning direction of a line-shaped pulse laserirradiation, when performing the polycrystallization laser annealing,onto a semiconductor layer which is an object of the polycrystallizationand at least part of both channel regions of the correction transistorand the driving transistor are located on the same line extending in adirection crossing the scanning direction of the pulse laser.
 4. A pixelcircuit, comprising: a selection transistor having one end connected toa data line, and a control end receiving a selection signal; acorrection transistor having one end connected to the other end of theselection transistor, and a control end connected to a first powersource at a predetermined voltage; a driving transistor having a controlend connected to the other end of the correction transistor, and one endconnected to a second power source functioning as a current supplysource; a storage capacitor having one end connected to the control endof the driving transistor, and the other end connected to a pulsevoltage line; and an emissive element for emitting light caused by acurrent flowing through the driving transistor, wherein the correctiontransistor is switched between on and off states in a process of turningon the driving transistor by changing a voltage value of the pulsevoltage line, thereby controlling a voltage of the control end of thedriving transistor when it is turned on, and the driving transistor andthe correction transistor are formed adjacent to each other, wherein thefirst power source and the second power source are the same powersource.
 5. A pixel circuit according to claim 4, wherein the data lineand the power source line extend in a vertical scanning direction, andthe correction transistor is formed between the data line and the powersource line.
 6. A pixel circuit according the claim 5, wherein thedriving transistor is formed on a side opposite to the correctiontransistor with the power source line located in between.
 7. A pixelcircuit according to claim 5, wherein the first power source and thesecond power source are the same power source.
 8. A pixel circuitaccording to claim 5, wherein the correction transistor and the drivingtransistor are p-channel transistors, and the pulse voltage line changesfrom a high level to a low level after the selection transistor isturned off.
 9. A pixel circuit according to claim 5, wherein activelayers of the correction transistor and the driving transistor areformed of polycrystalline semiconductor obtained by polycrystallizationlaser annealing, and a channel length direction of the correctiontransistor and a channel length direction of the driving transistor aredisposed in parallel to a scanning direction of a line-shaped pulselaser irradiation, when performing the polycrystallization laserannealing, onto a semiconductor layer which is an object of thepolycrystallization and at least part of both channel regions of thecorrection transistor and the driving transistor are located on the sameline extending in a direction crossing the scanning direction of thepulse laser.
 10. A pixel circuit, comprising: a selection transistorhaving one end connected to a data line, and a control end receiving aselection signal; a correction transistor having one end connected tothe other end of the selection transistor, and a control end connectedto a first power source at a predetermined voltage; a driving transistorhaving a control end connected to the other end of the correctiontransistor, and one end connected to a second power source functioningas a current supply source; a storage capacitor having one end connectedto the control end of the driving transistor, and the other endconnected to a pulse voltage line; and an emissive element for emittinglight caused by a current flowing through the driving transistor,wherein the correction transistor is switched between on and off statesin a process of turning on the driving transistor by changing a voltagevalue of the pulse voltage line, thereby controlling a voltage of thecontrol end of the driving transistor when it is turned on, and thedriving transistor and the correction transistor are formed adjacent toeach other, wherein the data line and the power source line extend in avertical scanning direction, and the correction transistor is formedbetween the data line and the power source line, wherein a data voltagefor turning on the correction transistor is supplied to the data linewhile the selection transistor is ON, a voltage corresponding to thedata voltage is stored at the control end of the driving transistor, theselection transistor is turned off thereafter, and the voltage of thecontrol end of the driving transistor is shifted by changing the voltageof the pulse voltage line in this state, thereby turning off thecorrection transistor and turning on the driving transistor to cause acurrent in accordance with the data voltage to flow into the drivingtransistor.
 11. A display device including a plurality of pixelsarranged in a matrix, each pixel comprising: a display element operatingin accordance with supplied power; a selection transistor having a firstconductive region connected to a data line, and a control end receivinga selection signal; a driving transistor having a first conductiveregion connected to a power source line for supplying power to thedisplay element; a correction transistor having a control end connectedto a first power source at a predetermined voltage, a first conductiveregion connected to a second conductive region of the selectiontransistor, and a second conductive region connected to a control end ofthe driving transistor; and a storage capacitor having a first electrodeconnected to the control end of the driving transistor and the secondconductive region of the correction transistor, and a second electrodeconnected to a pulse voltage line; wherein in accordance with theoperation threshold thereof, the correction transistor controls, inaccordance with a change in a voltage of the control end of the drivingtransistor in response to a change in a voltage of the pulse voltageline, the voltage of the control end of the driving transistor when thedriving transistor turns on, the correction transistor and the drivingtransistor are formed as transistors of the same conductivity type, andat least a channel region of each of the correction transistor and thedriving transistor is formed of a semiconductor layer polycrystallizedthrough laser annealing, and the channel regions thereof are disposed inclose proximity to each other, wherein the correction transistorincludes an active layer formed between the data line and the powersource line to extend partially underlying at least one of these lines.12. A display device according to claim 11, wherein a channel lengthdirection of the correction transistor and a channel length direction ofthe driving transistor are disposed in parallel to a scanning directionof a line-shaped pulse laser irradiated upon the polycrystallizationlaser annealing, and at least part of both channel regions of thecorrection transistor and the driving transistor are located on the sameline extending in a direction perpendicular to the scanning direction ofthe pulse laser.
 13. A display device according to claim 11, wherein thechannel region of the correction transistor has portions differing inchannel width in the channel length direction thereof.
 14. A displaydevice including a plurality of pixels arranged in a matrix, each pixelcomprising: a display element operating in accordance with suppliedpower; a selection transistor having a first conductive region connectedto a data line, and a control end receiving a selection signal; adriving transistor having a first conductive region connected to a powersource line for supplying power to the display element; a correctiontransistor having a control end connected to a first power source at apredetermined voltage, a first conductive region connected to a secondconductive region of the selection transistor, and a second conductiveregion connected to a control end of the driving transistor; and astorage capacitor having a first electrode connected to the control endof the driving transistor and the second conductive region of thecorrection transistor, and a second electrode connected to a pulsevoltage line; wherein in accordance with an operation threshold thereof,the correction transistor controls, in accordance with a change in avoltage of the control end of the driving transistor in response to achange in a voltage of the pulse voltage line, the voltage of thecontrol end of the driving transistor when the driving transistor turnson, the correction transistor and the driving transistor are formed astransistors of the same conductivity type, and at least part of anactive layer of the correction transistor is formed below the powersource line with an insulating layer disposed in between.
 15. A displaydevice according to claim 14, wherein the first power source is alsoused as the power source line, and the control end of the correctiontransistor connected to the power source line is formed between theactive layer of the correction transistor and a layer of the powersource line.
 16. A display device according to claim 14, wherein thechannel region of the correction transistor has portions differing inchannel width in the channel length direction thereof.
 17. A displaydevice according to claim 14, wherein the correction transistor includesan active layer formed between the data line and the power source lineto extend partially underlying at least one of these lines.